/************************************************Copyright(c)

***********************************
**                                   shenzhen  suosemi electronics Co,Ltd.
**                                   
**                                   http://www.suosemi.cn
**
**--------------------File Info------------------------------------------------------------

----
** File Name:                  sxdriver.h
** subversion number:          147
**----------------------------------------------------------------------------------------
********************************************************************************************

****/

#ifndef _sxDRIVER_H
#define _sxDRIVER_H
#define sx_1615

#define _sxFUNC_H_


#define CCS_RX  0
#define CCS_TX  1

#define FREQ2CHREG(freq)   ((freq-7600)/5)
#define CHREG2FREQ(ch)   (ch*5+7600)

// only used for engineering normally!

//extern UINT8 sxF_GetGoodChannel(UINT8 mode);

#define _sxCOMMON_H_


#define sxD_16xxAPI	__declspec(dllimport)	

#define S_XDATA 
#define S_IDATA
#define S_BIT unsigned char
#define S_SBIT unsigned char
#define S_CODE
#define S_SFR unsigned char

#define sxD_MODE_SLEEP      0     
#define sxD_MODE_WAKEUP     1
#define sxD_MODE_DEFAULT    2
// RX / TX value is using upper 8 bit

#define sxD_MODE_RX         0x8000
#define sxD_MODE_TX         0x4000
// AM / FM value is using lower 8 bit 
// need to check datasheet to get right bit 
#define sxD_MODE_FM         0x0000
#define sxD_MODE_AM         0x40

#define BAND_FM		0
#define BAND_AM		1
// tune
#define sxD_FSTEP_50KHZ      0
#define sxD_FSTEP_100KHZ      1
#define sxD_FSTEP_200KHZ      2
// output format
#define sxD_OUTPUT_ANALOG     0
#define sxD_OUTPUT_IIS        1

// stereo mode
#define sxD_TX_AUDIO_MONO              0x10
#define sxD_TX_AUDIO_STEREO            0x00

#define sxD_RX_AUDIO_MONO              0x20
#define sxD_RX_AUDIO_STEREO            0x00

#define  sxD_CONFIG_MONO               0x01
#define  sxD_CONFIG_MUTE			   0x02	
#define  sxD_CONFIG_SOFTCLIP		   0x03
#define  sxD_CONFIG_AUTOAGC			   0x04
#define  sxD_CONFIG_AGCGAIN			   0x05	

#define  sxD_CONFIG_EQUALIZER		   0x06	
#define  sxD_CONFIG_VOLUME			   0x07          
#define	 sxD_CONFIG_BASS_QUALITY       0x08
#define  sxD_CONFIG_BASS_FREQ		   0x09
#define  sxD_CONFIG_BASS_GAIN		   0x0a
#define  sxD_CONFIG_MID_QUALITY        0x0b
#define  sxD_CONFIG_MID_FREQ           0x0c
#define  sxD_CONFIG_MID_GAIN           0x0d
#define  sxD_CONFIG_TREBLE_FREQ        0x0e
#define  sxD_CONFIG_TREBLE_GAIN        0x0f

#define  sxD_ENABLE_EQUALIZER          0x10
#define  sxD_DISABLE_EQUALIZER         0x00


#define  sxD_CONFIG_AUDIOPEAK_DEV      0x11
#define  sxD_CONFIG_PILOT_DEV          0x12
#define  sxD_CONFIG_RDS_DEV            0x13

// input format
#define sxD_INPUT_ANALOG     0
#define sxD_INPUT_IIS        1

// i2s mode
#define sxD_I2S_RX_ANALOG   0x00
#define sxD_I2S_RX_DIGITAL  0x40
#define sxD_I2S_TX_ANALOG   0x00
#define sxD_I2S_TX_DIGITAL  0x20

//i2s clock data rate
#define sxD_I2S_DATA_RATE_32K  0x00
#define sxD_I2S_DATA_RATE_40K  0x10
#define sxD_I2S_DATA_RATE_44K  0x20
#define sxD_I2S_DATA_RATE_48K  0x30

//i2s clock Bit Wise
#define sxD_I2S_BIT_8    0x00
#define sxD_I2S_BIT_16   0x40
#define sxD_I2S_BIT_24   0x80
#define sxD_I2S_BIT_32   0xc0

//i2s Control mode
#define sxD_I2S_MASTER   1
#define sxD_I2S_SLAVE    0

//i2s Control mode
#define sxD_I2S_MSB   0x00
#define sxD_I2S_I2S   0x01
#define sxD_I2S_DSP1  0x02
#define sxD_I2S_DSP2  0x03
#define sxD_I2S_LSB   0x04

#define sxD_EQUALIZE_BASS	0x00
#define sxD_EQUALIZE_MID	0x01
#define sxD_EQUALIZE_TREBLE 0x02
// RDS, TMC
#define sxD_EUROPE_FLEXIBILITY_DISABLE  0
#define sxD_EUROPE_FLEXIBILITY_ENABLE   1
#define sxD_RDS_OFF              0
#define sxD_RDS_ON               1
#define sxD_RDS_BUFFER_NOT_READY 0
#define sxD_RDS_BUFFER_READY     1


#define CHIPID_sx1000	0x00
#define CHIPID_sx1005	0x20
#define CHIPID_sx1005B1 0x21
#define CHIPID_sx1006	0x30
#define CHIPID_sx1007B1 0x11
#define CHIPID_sx1007	0x10
#define CHIPID_sx1006A1 0x30
#define CHIPID_sx1006B1 0x31
#define CHIPID_g1016   0xe0
#define CHIPID_sx1016_1 0xb0
#define CHIPID_sx1015   0xa0
#define CHIPID_sx1065   0xa0
#define CHIPID_sx1067   0xd0
#define CHIPID_sx1065N  0xa0
#define CHIPID_sx1615   0x40
#define CHIPID_sx1025   0x80

#define RDS_INT_ENABLE  1
#define RDS_INT_DISABLE 0
//For antena impedance match
#define sxD_HIGH_IMPEDANCE 		1
#define sxD_LOW_IMPEDANCE 		0


typedef unsigned char  UINT8;             
//typedef char           INT8;              
typedef unsigned short UINT16;            
//typedef short          INT16;    
typedef unsigned long   UINT32;            
//typedef signed   long   INT32;  
typedef float          FP32;              
typedef double         FP64;              
#define  sxD_C2BYTE(a,b)  (a<<24 | b<<16)

#define _sxCONFIG_H_

/*******************************************************************************************

***
// flag configuration
********************************************************************************************

***/
/************************MCU platform selection*****************/
// Target compiler: 8051 (Keil or others)
// #define sxD_C51
// Target compiler: ARM (ADS or others)
//#define sxD_ARM_ADS


/***************************** CHIP ID ******************************/
//#define sx_1000
//#define sx_1005
//#define sx_1005B

//#define sx_1007
//#define sx_1007B

//#define sx_1006A0
//#define sx_1006A1

/********************* country selection**************/
#define COUNTRY_CHINA			0
#define COUNTRY_USA				1
#define COUNTRY_JAPAN			2
/************************EDN******************************/


/*******************************************************************************************

***
// limitation configuration 
********************************************************************************************

***/

#define sxD_READ_RSSI_DELAY    10


// auto scan
#define sxD_MP_THRESHOLD       0x28   

#define assert(str)
#define sxD_LOG(a)
#define sxD_LOGA(a,b)
#define sxD_LOGB(a,b)
#define sxD_LOGHEX(a,b)



#define _sxREG_H_



#define SYSTEM1		0x00
#define SYSTEM2		0x00
#define CH			0x01
#define CH_STEP		0x00
#define RDSD0		0x08
#define PAG_CAL		0x1f
#define CID2		6

#define RDSEN		0x80
#define TXREQ       0x20
#define CH_CH      0x03
#define RDSTXRDY   0x04


#define _sxSYS_H_
// external driver interface 
// logical layer
/*****************************************************************************
Driver API Macro Definition
*****************************************************************************/
#define sxM_SetCrystal(CrystalCapLoad)    \
        sxD_WriteReg(REG_VGA, sxD_ReadReg(REG_VGA) | (CrystalCapLoad & 0xcf))     
#define sxM_SetAudioInputImpedance(AudioImpendance) \
        sxD_WriteReg(REG_VGA, sxD_ReadReg(REG_VGA) | (AudioImpendance & 0x3f))   
#define sxM_ResetToDefault() \
        sxD_WriteReg(SYSTEM2, SWRST) 
#define sxM_SetFMWorkingMode(Modemask, Mode) \
        sxD_WriteReg(SYSTEM1, Mode|(sxD_ReadReg(SYSTEM1) &~ Modemask)
#define sxM_EnableAGC() \
        sxD_WriteReg(TXAGC_GAIN, ~ TAGC_GAIN_SEL&(sxD_ReadReg(TXAGC_GAIN) )
#define sxM_DisableAGC()\
	    sxD_WriteReg(TXAGC_GAIN,   1|(TAGC_GAIN_SEL|(sxD_ReadReg(TXAGC_GAIN)) )
#define sxM_EnableSoftClip() \
	    sxD_WriteReg(TXAGC_GAIN,    TX_SFTCLPEN |(sxD_ReadReg(TXAGC_GAIN)) )
#define sxM_DisableSoftClip() \
	    sxD_WriteReg(TXAGC_GAIN,    ~TX_SFTCLPEN &(sxD_ReadReg(TXAGC_GAIN)) )
#define sxM_GetMonoMode() \
	    sxD_WriteReg(STATUS1) & ST_MO_RX
#define sxM_SetRxThreshold(db) \
        sxD_WriteReg(CCA, db);
#define sxM_SetAudioOutFormatIIS() \
        sxD_WriteReg(CCA, (sxD_READ(CCA) | RXI2S));
#define sxM_SetAudioOutFormatAnalog() \
        sxD_WriteReg(CCA, (sxD_READ(CCA) & ~RXI2S));
#define sxM_SetAudioInFormatIIS() \
        sxD_WriteReg(CCA, (sxD_READ(CCA) | RXI2S));
#define sxM_SetAudioInFormatAnalog() \
        sxD_WriteReg(CCA, (sxD_READ(CCA) & ~RXI2S));
#define sxD_AntenaInputImpedance(impendance) \
        sxD_WriteReg(77, impendance);


#define sxD_READ(adr)    sxD_ReadReg(adr)
#define sxD_WRITE(adr, value)  sxD_WriteReg(adr, value)

extern UINT8 S_XDATA RSSIn;
extern UINT8 S_XDATA Rssinarray[4];
extern UINT8 S_XDATA sxd_Country;
extern UINT16 S_XDATA sxD_CH_START;
extern UINT16 S_XDATA sxD_CH_STOP;
extern UINT8 S_XDATA sxD_CH_STEP;
extern UINT16 S_XDATA sxD_CH_AM_START;
extern UINT16 S_XDATA sxD_CH_AM_STOP;
extern UINT8 S_XDATA sxD_CH_AM_STEP;
extern UINT8 S_XDATA sxd_Band;
extern UINT8 S_XDATA AmCCAIncr;
extern UINT8 S_XDATA sxd_ChipIndex_1015;
extern UINT8 S_XDATA sxd_ChipIndex_1615;

/*
  System General Control 
*/
extern void sxD_Delay(UINT16 ms) ;
extern UINT8 sxD_Init(void) ;
extern void sxD_TuneToCH(UINT16 ch) ;
extern void sxD_SetSysMode(UINT16 mode) ;
extern void sxD_SetCountry(UINT8 country) ;



#define sx_TX
#define _sxTX_H_


extern void   sxD_TXSetPower(UINT8 gain);
extern void   sxD_TXConfigAudio(UINT8 optiontype, UINT8 option );

#define sx_RDS

#define _sxRDS_H_

extern UINT8 sxD_RDSEnable(UINT8 on) ;
extern UINT8 sxD_RDSCheckBufferReady(void) ;
extern void sxD_RDSLoadData(UINT8 *rdsRawData, UINT8 upload) ;
#endif
